1. Technical Field
This invention relates generally to memory devices, and more particularly, to a memory array incorporating memory-diodes.
2. Background Art
Generally, memory devices associated with computers and other electronic devices are employed to store and maintain information for the operation thereof. Typically, such a memory device includes an array of memory cells, wherein each memory cell can be accessed for programming, erasing, and reading thereof. Each memory cell maintains information in an “off” state or an “on” state, also referred to as “0” and “1” respectively, which can be read during the reading step of that memory cell.
As such electronic devices continue to be developed and improved, the amount of information required to be stored and maintained continues to increase. FIG. 1 illustrates a type of memory cell known as a memory-diode 30, which includes advantageous characteristics for meeting these needs. The memory-diode 30 includes an electrode 32, a superionic layer 34 on the electrode 32, an active layer 36 on the superionic layer 34, and an electrode 38 on the active layer 36. Initially, assuming that the memory-diode 30 is unprogrammed, in order to program the memory-diode 30, a negative voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory-diode 30 from a higher to a lower electrical potential in the forward direction of the memory-diode 30 (see FIG. 2, a plot of memory diode current vs. electrical potential applied across the memory-diode 30). This potential is sufficient to cause copper ions to be attracted from the superionic layer 34 toward the electrode 38 and into the active layer 36 (A), causing the active layer 36 (and the overall memory-diode 30) to be in a (forward) low-resistance or conductive state. Upon removal of such potential (B), the copper ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory-diode 30) remain in a conductive or low-resistance state.
FIG. 3 illustrates the read step of the memory-diode 30 in its programmed (conductive) state. An electrical potential Vr (the “read” electrical potential) is applied across the memory-diode 30 from a higher to a lower electrical potential in the forward direction of the memory-diode 30. This electrical potential is sufficient to overcome the threshold voltage Vt of the inherent diode characteristic of the memory-diode 30, but is less than the electrical potential Vpg applied across the memory-diode 30 for programming (see above). In this situation, the memory-diode 30 will readily conduct current, which indicates that the memory-diode 30 is in its programmed state.
In order to erase the memory-diode (FIG. 4), a positive voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory-diode 30 from a higher to a lower electrical potential in the reverse direction of the memory-diode 30. This potential is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34, causing the active layer 36 (and the overall memory-diode 30) to be in a high-resistance or substantially non-conductive state (see FIG. 5, illustrating application of electrical potential Ver across the memory-diode 30). This state remains upon removal of such potential from the memory-diode 30.
FIG. 6 illustrates the read step of the memory-diode 30 in its erased (substantially non-conductive) state. The electrical potential Vr is again applied across the memory-diode 30 from a higher to a lower electrical potential in the forward direction of the memory-diode 30, as described above. With the active layer 34 (and memory-diode 30) in a high-resistance or substantially non-conductive state, the memory-diode 30 will not conduct significant current, which indicates that the memory-diode 30 is in its erased state.
FIG. 7 illustrates a memory-diode array 40 which incorporates memory-diodes 30 of the type described above. As illustrated in FIG. 7, the memory-diode array 40 includes a first plurality 42 of parallel conductors (bit lines) BL0, BL1, . . . BLn, and a second plurality 44 of parallel conductors (word lines) WL0, WL1, . . . WLn overlying and spaced from, orthogonal to, and crossing the first plurality of conductors 42. A plurality of memory-diodes 30 (3000, 3010, 30n0, 3001, 3011, 30n1, 300n, 301n, 30nn shown) of the type described above are included. Each memory-diode 30 connects a conductor BL of the first plurality 42 thereof with a conductor WL of the second plurality 44 thereof at the intersection of those conductors, with the memory-diode 30 thereof in a forward direction from the conductor BL of the first plurality 42 thereof to the conductor WL of the second plurality 44 thereof. For example, as shown in FIG. 7, memory-diode 3000 connects conductor BL0 of the first plurality of conductors 42 with conductor WL0 of the second plurality of conductors 44 at the intersection of those conductors BL0, WL0, memory-diode 3010 connects conductor BL1 of the first plurality of conductors 42 with conductor WL0 of the second plurality of conductors 44 at the intersection of those conductors BL1, WL0, etc.
In order to program a selected memory diode (FIG. 7), for example selected memory-diode 3000, the voltage V1 applied to the conductor BL0 must be Vpg greater than the voltage V2 applied to the conductor WL0. However, in order to avoid an undesired disturb condition of any of the other memory-diodes in the array 40, the following approach can be undertaken. In furtherance thereof, a voltage V3 greater than voltage V2 is applied to each of the conductors WL1-WLn, with the difference between voltage V1 and voltage V3 being less than Vpg. Additionally, a voltage V4 greater than voltage V2 is applied to each of the conductors BL1-BLn, with the difference between voltage V4 and voltage V2 being less than Vpg. Furthermore, voltages V3 and V4 can be chosen as equal, so that each of the great majority of memory-diodes in the array 40, i.e., those memory-diodes not connected to either conductor BL0 or conductor WL0, has substantially no electrical potential applied thereacross, so as to minimize current leakage therethrough.
However, it has been found that the threshold voltage of a programmed memory-diode may well be very low, leading to problems as will now be described.
As noted above, during the programming of the selected memory-diode 3000, the selected memory diode-3000 has applied thereacross Vpg, i.e., (V1-V2) in the forward direction of that memory-diode 3000. Meanwhile (FIGS. 7 and 8), each of the other memory-diodes 3001-300n connected to the conductor BL0 has applied thereacross (V1-V3) in the forward direction, which is less than Vpg. However, in the case of programmed memory-diodes within the group of memory-diodes connected to the conductor BL0, with the threshold voltage thereof being very low, electrical potential (V1-V3) applied across each of these programmed memory-diodes in the forward direction thereof may well be sufficient to overcome their respective threshold voltages Vt so as to allow substantial current to pass therethrough. Meanwhile (FIGS. 7 and 8), each of the other memory-diodes connected to the conductor WL0 has applied thereacross (V4-V2), which is less than Vpg. Again, in the case of the programmed memory-diodes within the group of memory-diodes 3010-30n0 connected to the conductor WL0, with the threshold voltage thereof being very low, electrical potential (V4-V2) applied across each of these programmed memory-diodes in the forward direction thereof may well be sufficient to overcome their respective threshold voltages Vt so as to allow substantial current to pass therethrough. It will be readily seen that this approach results in significant current leakage during the programming of a selected memory-diode 3000, resulting in significant degradation in performance of the memory-diode array 40.
What is needed is an approach which overcomes the above-cited problems.